1. Field of Invention
This invention relates to semiconductor memories and in particular split gate flash memory cells.
2. Description of Related Art
Split gate flash memory technology requires a relatively large cell size compared to other type memory technologies. This is in part caused by misalignment problems and not being able to take advantage of self alignment techniques. Some designs of flash memory cells have multiple storage bits per each memory cell to accommodate the increased demand storage density, but this usually comes with an increased program current.
In U.S. Pat. No. 5,679,970 (Hartmann) a triple gate flash EPROM device is shown wherein two gate stacks each including a floating gate share a source with a control gate partially overlapping the gate stacks. In U.S. Pat. No. 5,508,955 (Zimmer et al.) is described a split gate EPROM cell with buried bit lines on either side of a storage cell. The source for the EPROM cell is in part a buried bit line on one side of the storage cell and the drain is in part a buried bit line on the other side of the cell In U.S. Pat. No. 5,440,158 (Sung-Mu) is shown an EPROM cell with dual sidewall floating gates. Source and drain regions are formed between and on either side of the floating gates and a control gate is formed over the floating gates. In U.S. Pat. No. 5,420,060 (Gill et al.) is shown a method for forming contact-free floating gate memory array with silicided buried bit lines and with a single step defined floating gates. In U.S. Pat. No. 5,067,108 (Jenq), an electrically conductive re-crystallized floating gate is disposed over an insulating area extending over a portion of a channel region and a drain region. A control gate partially overlaps the floating gate and extends over a portion of a source region.
With the demands for increased density for flash memory chips, it is important to create a small cell size that is easy to shrink, has multiple storage capability and requires proportionately small program current. The demand for increased density will require a solution to the misalignment problem in conventional split gate flash memories, and the minimizing of requirements for metalization and contact areas. To deal with the density requirement a cell architecture is required that has a plurality of floating gates with self alignment to produce source and drain areas that are in part a portion of buried bit lines and a control gate that extends beyond the cell to form in part a word line for the flash memory. Doing these items of improvement can produce an architecture for a split gate flash memory cell that will allow the cell to be reduced in size producing a higher flash memory density.
In this invention polysilicon sidewalls are used as floating gates for a flash memory. The sidewalls partially extend over ion implanted bit lines that operate as sources and drains in performing flash memory read, write and erase operations. Polysilicon control gates are formed over the sidewalls in an orthogonal orientation extending the length of a flash memory word line.
The polysilicon sidewalls are formed on the sides of silicon nitride blocks. Buried bit lines extending the length of a column of silicon nitride blocks are ion implanted between columns of silicon nitride blocks using the silicon nitride blocks with the polysilicon sidewalls as a mask. The buried bit lines are implanted between columns of silicon nitride blocks with the polysilicon sidewalls. The bit line implanted between adjacent columns of silicon nitride blocks extends the length of a flash memory column and lie partially under the sidewalls attached to the silicon nitride blocks which are located on either side of the implanted bit lines.
Once the bit lines are implanted, the silicon nitride blocks are removed leaving two polysilicon sidewalls on opposite sides of the removed silicon nitride blocks. The two polysilicon sidewalls are separated by the space left by the removed silicon nitride block and form a part of two columns of flash memory cells that are independent of each other. The polysilicon sidewalls are insulated with a dielectric layer and a control gate is formed over the sidewalls orthogonal to the buried bit lines and extending the length of a word line of the flash memory.
At each site of the silicon nitride blocks there are two polysilicon sidewalls left standing once the silicon nitride blocks have been removed. The sidewalls are used as floating gates and form two independent flash memory cells. A first of the two sidewalls (hereafter called xe2x80x9ccell 1xe2x80x9d) partially covers a first bit line, and the second of the two sidewalls (hereafter called xe2x80x9ccell 2xe2x80x9d) partially covers a second bit line. One of the two bit lines at each site acts as a source and the other a drain, and each bit line is shared with a sidewall cell at an adjacent site.
Cell 1 is programmed by applying a first positive voltage to the control gate overlaying the row of cells containing cell 1 and cell 2. A second positive voltage is applied to the bit line (hereafter called xe2x80x9cbit line 2xe2x80x9d) running under the edge of the sidewall forming cell 2, and zero volts is applied to the bit line 1 running under the edge of the sidewall forming cell 1 (hereafter called xe2x80x9cbit line 1xe2x80x9d). Bit line 2 acts like a source supplying source side hot carriers to program a charge onto the floating gate of cell 1. Cell 2 is programmed by applying the same first positive voltage to the control gate as used for cell 1. The same second positive voltage is applied to bit line 1 running under the edge of the sidewall forming cell 1, and zero volts is applied to bit line 2. Bit line 1 acts like a source supplying source side hot carriers to program a charge onto the floating gate of cell 2.
To read cell 1, a third positive voltage less in magnitude than the first positive voltage is applied to the control gate. A fourth positive voltage less in magnitude than the third positive voltage is applied to bit line 2 acting as a drain, and bit line 1 is connected to zero volts through a sense amplifier. To read cell 2 the third positive voltage is applied to the control gate. The fourth positive voltage is applied to bit line 1 acting as a drain; and bit line 2 is connected to zero volts through a sense amplifier. To erase cells 1 and 2 a fifth positive voltage greater then the first positive voltage and high enough in amplitude to invoke Fowler-Nordheim tunneling is applied to bit line 1 and 2 with circuit ground connected to the control gate.